Test generation for combinational circuits in Java Generator barcode 3 of 9 in Java Test generation for combinational circuits

Test generation for combinational circuits generate, create 39 barcode none on java projects Microsoft .NET Micro Framework c1 G2 x2 x3 x4 x5 06 6 06 6. 16 16. c5 c6 G4 c 10. Figure 4.40 Targeting c3 SA1 starting with an incompletely speci ed vector for c8 SA1 Higher fault coverage ca n often be obtained by selecting another fault as a target fault that may be detected by further specifying the values of the given incompletely speci ed vector and performing test generation for that fault. Consider an intermediate stage during test generation for the circuit shown in Figure 4.40.

Assume that previously generated vectors have detected all the faults except {c3 SA1, c8 SA1}. Assume that at this stage, fault c8 SA1 is targeted and the incompletely speci ed vector (x, 0, x, 0, 1) is generated. Now, we can select the only remaining fault in the fault list, c3 SA1, as the surrogate target fault and attempt test generation starting with the above vector.

Figure 4.40 shows the circuit with this target fault and the above vector. PODEM can now be applied to further specify the components of the above vector to generate a test for the secondary target fault.

The reader can verify that this test generation will be successful and generate a fully speci ed vector, (1, 0, 1, 0, 1) which will detect c3 SA1 in addition to c8 SA1.. Test generation for reduced heat and noise during test Attainment of high fault coverage has traditionally been the main objective of test generation techniques. In recent years, reducing the heat dissipated during test application has become an important auxiliary objective. The importance of this problem is illustrated by the example circuit reported in Zorian (1993), where heat dissipation during test application was signi cantly higher (100 200%) than during the circuit s normal operation.

This increase can be attributed to several factors. First, signi cant correlation exists between successive vectors. 4.9 Test generation for reduced heat and noise during test applied to a block of co mbinational logic during its normal operation. In contrast, the correlation between consecutive test vectors generated by a test generator is very low, since a test is generated for a given target fault without any consideration of the previous vector in the test sequence. Second, the use of DFT techniques can further decrease the correlation between successive test vectors.

For example, this is true for the scan DFT technique (see 11) since the values applied during successive clock cycles at the state inputs of a logic block represent shifted values of scan test vectors and circuit responses. This is even more true for built-in self-test techniques which typically employ random pattern generators to generate test sequences, where the correlation between consecutive vectors is provably small (see 12; Section 12.2).

Finally, circuit miniaturization requires the package size to be reduced to aggressively match the average heat dissipation during the circuit s normal operation. It is important to ensure that heat dissipation during test application does not destroy a chip during test. It is also important to reduce switching noise during test application, since excessive switching noise may cause a logical error in a fault-free chip leading to an unnecessary loss of yield.

In this section, we discuss a technique to generate sequences of test vectors that provide high fault coverage while minimizing heat dissipation and switching noise during test application (Wang and Gupta, 1998). The technique discussed here focuses on combinational circuits; techniques for scan circuits are discussed in 11 (Section 11.6.

2).. Preliminaries In the following, the CU T is assumed to be a CMOS digital circuit. Heat dissipation in CMOS can be divided into static and dynamic. Static dissipation is due to leakage currents that currently have small magnitudes in digital CMOS circuits.

Hence, for such circuits, the dynamic dissipation is the dominant term. Dynamic dissipation occurs at a node when it switches from 0 1 (or from 1 0) and is typically divided into two components caused by short-circuit current and charge/discharge current, respectively. The former is caused by a current pulse that ows from power supply to ground when both nMOS and pMOS transistors are simultaneously on during switching.

The charge/discharge current is the current that charges and discharges the output capacitive load and typically dominates dynamic dissipation. Under the zero-delay model (i.e.

, when the gates are assumed to switch with zero delay) and ignoring logic hazards, the dynamic power dissipation in the circuit can be approximated as described next. Let P pr and P be the previous and the current test vectors applied to the CUT. Let pr (c ) and v(c ), respectively, be the values implied at a line c by these two vectors.

v i i i The amount of heat dissipated due to the application of test vector P is approximately proportional to.
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