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7. generate, create none none in none data matrix Figure 7-12 Simple switchi none for none ng circuit for a transistor in the common-emitter configuration: (a) biasing circuit; (b) collector characteristics and load line for the circuit, with cutoff and saturation indicate d ; (c) operating regimes of a BJT.. Barcode FAQs 5 Ml loo ko 40 V. /" = D.I in A -10V (a) (b). VBE (forward bias). normal active saturation VBC (forward bias). cutoff inverted we have the normal active mode; the opposite gives us the mverted mode of operation. If both junctions are reverse biased, we get cutoff, leading to a very high impedance state of the BJT; if both junctions are forward biased, we have saturation and a low impedance state..

7.6.1 Cutoff If the emitter junction is reverse biased in the cutoff regime (negative iB), we can approximate the excess hole concentrations at the edges of the reversebiased emitter and collector junctions as &pE _ Apc. Pn Pn - -1. 7-44). Bipolar Junction Transistors which implies p(xn) - 0. T none for none he excess hole distribution in the base is approximately constant at p , with some slope to the distribution at each edge to account for the reverse saturation current in the junctions.The base current iB can be approximated for a symmetrical transistor on a charge storage basis as -qApnWblTp.

In this calculation a negative excess hole concentration corresponds to generation in the same way that a positive distribution indicates recombination. This expression is also obtained by applying Eq. (7-44) to Eq.

(7-19) with an approximation from Table 7-1. Physically, a small saturation current flows from n to p in each reverse-biased junction, and this current is supplied by the base current iB (which is negative when flowing into the base of a p-n-p device according to our definitions). A more general evaluation of the currents can be obtained from the Ebers-Moll equations by applying Eq.

(7-44) to Eq. (7-34): < = ~hs + <x/"cs = - ( 1 ~ aN)IES ic = -a.NIES + Ics = ( - /)^C5 *B JE ~ k = " ( I ~ UNVES - ( - /) cs.

(7-45a) (7-45b). (7-45c). If the short-circuit satur ation currents IES and Ics are small and a^ and a, are both near unity, these currents will be negligible and the cutoff regime will closely approximate the "off" condition of an ideal switch. The equivalent circuit corresponding to Eq. (7-45) is illustrated in Fig.

7-13b. 7.6.

2 Saturation. The saturation regime begi none none ns when the reverse bias across the collector junction is reduced to zero, and it continues as the collector becomes forward biased. The excess hole distribution in this case is illustrated in Fig. 7-14.

The device is saturated when Apc = 0, and forward bias of the collector junction. " - .v)//,s Figure 7 - 1 3 The cutoff none none regime of a p-n-p transistor: (a) excess hole distribution in the base region with emitter and collector junctions reverse biased; (b) equivalent circuit corresponding toEq. (7-45)..

7 . Figure 7-14 Excess hole di none for none stribution in the base of a saturated transistor: (a) the beginning of saturation; (b) oversaturation.. WEB positive) (K cs zero). WFB positive) ( Vcu positive). (Fig. 7- 14b) leads to a p ositive A/ c, driving the device further into saturation. With the load line fixed by the battery and the 5-kO resistor in Fig.

7-12, saturation is reached by increasing the base current iB. We can see how a large value of iB leads to saturation by applying the reasoning of charge control to Fig. 7-14.

Since a certain amount of stored charge is required to accommodate a given iB (and vice versa), an increase in iB calls for an increase in the area under the hp(x ) distribution. In Fig. 7-14a the device has just reached saturation, and the collector junction is no longer reverse biased.

The implication of this condition for the circuit of Fig. 7-12 is easy to state. Since the emitter junction is forward biased and the collector junction has zero bias, very little voltage drop appears across the device from collector to emitter.

The magnitude of -vCE is only a fraction of a volt. Therefore, almost all of the battery voltage appears across the resistor, and the collector current is approximately 40 V/5 kH = 8 mA. As the device is driven deeper into saturation (Fig.

7-14b), the collector current stays essentially constant while the base current increases. In this saturation condition the transistor approximates the "on" state of an ideal switch. Whereas the degree of "oversaturation" (indicated by the shaded area in Fig.

7-14b) does not affect the value of ic significantly, it is important in determining the time required to switch the device from one state to the other. For example, from previous experience we expect the turn-off time (from saturation to cutoff) to be longer for larger values of stored charge in the base. We can calculate the various charging and delay times from Eq.

(7-43). Detailed calculations are somewhat involved, but we can simplify the problem greatly with approximations of the type used in 5 for transient effects in p-n junctions..

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