Page 44 Tuesday, April 16, 2002 9:12 AM in .NET Generation European Article Number 13 in .NET Page 44 Tuesday, April 16, 2002 9:12 AM Page 44 Tuesday, April 16, 2002 9:12 AM using visual studio .net togenerate ean-13 supplement 2 with web,windows application Web app Section 10.2 Classification of Digital Systems CLK In R1 Cin Combinational Logic Figure 10.1 Synchronous interconnect methodology. R2 Cout Out R2 which synch visual .net EAN-13 Supplement 5 ronizes the output with the clock. In a sense, the certainty period of signal Cout, or the period where data is valid is synchronized with the system clock, which allows register R2 to sample the data with complete confidence.

The length of the uncertainty period, or the period where data is not valid, places an upper bound on how fast a synchronous interconnect system can be clocked. 10.2.

2 Mesochronous interconnect. A mesochronous signal is one that has the same frequency but an unknown phase offset with respect to the local clock ( meso from Greek is middle). For example, if data is being passed between two different clock domains, then the data signal transmitted from the first module can have an unknown phase relationship to the clock of the receiving module. In such a system, it is not possible to directly sample the output at the receiving module because of the uncertainty in the phase offset.

A (mesochronous) synchronizer can be used to synchronize the data signal with the receiving clock as shown below. The synchronizer serves to adjust the phase of the received signal to ensure proper sampling..

Block A R1 Interconnect Delay D3 D2 R2 Block B D4 ClkB PD/ Control ClkA Figure 10.2 Mesochronous communication approach using variable delay line. In Figure 10.2 , signal D1 is synchronous with respect to ClkA. However, D1 and D2 are mesochronous with ClkB because of the unknown phase difference between ClkA and ClkB and the unknown interconnect delay in the path between Block A and Block B.

The role of the synchronizer is to adjust the variable delay line such that the data signal D3 (a delayed version of D2) is aligned properly with the system clock of block B. In this example, the variable delay element is adjusted by measuring the phase difference between the received signal and the local clock. After register R2 samples the incoming data during the certainty period, then signal D4 becomes synchronous with ClkB.

10.2.3 Plesiochronous Interconnect.

A plesiochrono VS .NET GTIN-13 us signal is one that has nominally the same, but slightly different frequency as the local clock ( plesio from Greek is near). In effect, the phase difference. Page 45 Tuesday, April 16, 2002 9:12 AM TIMING ISSUES IN DIGITAL CIRCUITS 10 . drifts in time visual .net EAN-13 Supplement 2 . This scenario can easily arise when two interacting modules have independent clocks generated from separate crystal oscillators.

Since the transmitted signal can arrive at the receiving module at a different rate than the local clock, one needs to utilize a buffering scheme to ensure all data is received. Typically, plesiochronous interconnect only occurs in distributed systems like long distance communications, since chip or even board level circuits typically utilize a common oscillator to derive local clocks. A possible framework for plesiochronous interconnect is shown in Figure 10.

3.. Clock C 1 Timing Recovery C3 Originating Module FIFO Receiving Module Clock C2 Figure 10.3 Plesiochronous communications using FIFO. In this digita l communications framework, the originating module issues data at some unknown rate characterized by C1, which is plesiochronous with respect to C2. The timing recovery unit is responsible for deriving clock C3 from the data sequence, and buffering the data in a FIFO. As a result, C3 will be synchronous with the data at the input of the FIFO and will be mesochronous with C1.

Since the clock frequencies from the originating and receiving modules are mismatched, data might have to be dropped if the transmit frequency is faster, and data can be duplicated if the transmit frequency is slower than the receive frequency. However, by making the FIFO large enough, and periodically resetting the system whenever an overflow condition occurs, robust communication can be achieved. 10.

2.4 Asynchronous Interconnect. Asynchronous s EAN-13 for .NET ignals can transition at any arbitrary time, and are not slaved to any local clock. As a result, it is not straightforward to map these arbitrary transitions into a synchronized data stream.

Although it is possible to synchronize asynchronous signals by detecting events and introducing latencies into a data stream synchronized to a local clock, a more natural way to handle asynchronous signals is to simply eliminate the use of local clocks and utilize a self-timed asynchronous design approach. In such an approach, communication between modules is controlled through a handshaking protocol to perform the proper ordering of commands..

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