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Layout Example in Microsoft Office Generating DataMatrix in Microsoft Office Layout Example

Example 2.1 Layout Example generate, create data matrix none with microsoft office projects Basic Infromation about Micro QR Code An example of a comp Microsoft Office datamatrix 2d barcode lete layout containing an inverter is shown in Figure 2.9. To help the visualization process, a vertical cross section of the process along the design center is included as well as a circuit schematic.

. chapter2.fm Page 56 Friday, January 18, 2002 8:59 AM GND In THE MANUFACTURING PROCESS 2 . Out (a) Layout A n p-substrate n+ (b) Cross section along A-A In p+ Field oxide GND Out (c) Circuit diagram Figure 2.9 A detailed layout example, including vertical process cross section and circuit diagram. It is left as an exe rcise for the reader to determine the sizes of both the NMOS and the PMOS transistors.. Packaging Integrated Data Matrix 2d barcode for None Circuits The IC package plays a fundamental role in the operation and performance of a component. Besides providing a means of bringing signal and supply wires in and out of the silicon die, it also removes the heat generated by the circuit and provides mechanical support. Finally, its also protects the die against environmental conditions such as humidity.

The packaging technology furthermore has a major impact on the performance and power-dissipation of a microprocessor or signal processor. This influence is getting more pronounced as time progresses by the reduction in internal signal delays and on-chip capacitance as a result of technology scaling. Up to 50% of the delay of a high-performance computer is currently due to packaging delays, and this number is expected to rise.

. chapter2.fm Page 57 Friday, January 18, 2002 8:59 AM Section 2.4 Packaging Integrated Circuits The search for highe Microsoft Office ECC200 r-performance packages with fewer inductive or capacitive parasitics has accelerated in recent years. The increasing complexity of what can be integrated on a single die also translates into a need for ever more input-output pins, as the number of connections going off-chip tends to be roughly proportional to the complexity of the circuitry on the chip. This relationship was first observed by E.

Rent of IBM (published in [Landman71]), who translated it into an empirical formula that is appropriately called Rent s rule. This formula relates the number of input/output pins to the complexity of the circuit, as measured by the number of gates. P = K G (2.

1). where K is the avera ge number of I/Os per gate, G the number of gates, the Rent exponent, and P the number of I/O pins to the chip. varies between 0.1 and 0.

7. Its value depends strongly upon the application area, architecture, and organization of the circuit, as demonstrated in Table 2.1.

Clearly, microprocessors display a very different input/output behavior compared to memories.. Table 2.1 Rent s con Microsoft Office Data Matrix 2d barcode stant for various classes of systems ([Bakoglu90]) Application Static memory Microprocessor Gate array High-speed computer (chip) High-speed computer (board) 0.12 0.

45 0.5 0.63 0.

25 K 6 0.82 1.9 1.

4 82. The observed rate of pin-count increase for integrated circuits varies between 8% to 11% per year, and it has been projected that packages with more than 2000 pins will be required by the year 2010. For all these reasons, traditional dual-in-line, through-hole mounted packages have been replaced by other approaches such as surface-mount, ballgrid array, and multichip module techniques. It is useful for the circuit designer to be aware of the available options, and their pros and cons.

Due to its multi-functionality, a good package must comply with a large variety of requirements. Electrical requirements Pins should exhibit low capacitance (both interwire and to the substrate), resistance, and inductance. A large characteristic impedance should be tuned to optimize transmission line behavior.

Observe that intrinsic integrated-circuit impedances are high. Mechanical and thermal properties The heat-removal rate should be as high as possible. Mechanical reliability requires a good matching between the thermal properties of the die and the chip carrier.

Long-term reliability requires a strong connection from die to package as well as from package to board.. chapter2.fm Page 58 Friday, January 18, 2002 8:59 AM THE MANUFACTURING PROCESS 2 . Low Cost Cost is a lways one of the more important properties. While ceramics have a superior performance over plastic packages, they are also substantially more expensive. Increasing the heat removal capacity of a package also tends to raise the package cost.

The least expensive plastic packaging can dissipate up to 1 W. Somewhat more expensive, but still cheap, plastic packages can dissipate up to 2W. Higher dissipation requires more expensive ceramic packaging.

Chips dissipating over 50 W require special heat sink attachments. Even more extreme techniques such as fans and blowers, liquid cooling hardware, or heat pipes, are needed for higher dissipation levels. Packing density is a major factor in reducing board cost.

The increasing pin count either requires an increase in the package size or a reduction in the pitch between the pins. Both have a profound effect on the packaging economics. Packages can be classified in many different ways by their main material, the number of interconnection levels, and the means used to remove heat.

In this short section, we can only glance briefly at each of those issues. 2.4.

1 Package Materials. The most common mate barcode data matrix for None rials used for the package body are ceramic and polymers (plastics). The latter have the advantage of being substantially cheaper, but suffer from inferior thermal properties. For instance, the ceramic Al2O3 (Alumina) conducts heat better than SiO2 and the Polyimide plastic, by factors of 30 and 100 respectively.

Furthermore, its thermal expansion coefficient is substantially closer to the typical interconnect metals. The disadvantage of alumina and other ceramics is their high dielectric constant, which results in large interconnect capacitances. 2.

4.2 Interconnect Levels. The traditional pack aging approach uses a two-level interconnection strategy. The die is first attached to an individual chip carrier or substrate. The package body contains an internal cavity where the chip is mounted.

These cavities provide ample room for many connections to the chip leads (or pins). The leads compose the second interconnect level and connect the chip to the global interconnect medium, which is normally a PC board. Complex systems contain even more interconnect levels, since boards are connected together using backplanes or ribbon cables.

The first two layers of the interconnect hierarchy are illustrated in the drawing of Figure 2.10. The following sections provide a brief overview of the interconnect techniques used at levels one and two of the interconnect hierarchy, followed by a short discussion of some more advanced packaging approaches.

Interconnect Level 1 Die-to-Package-Substrate For a long time, wire bonding was the technique of choice to provide an electrical connection between die and package. In this approach, the backside of the die is attached to the substrate using glue with a good thermal conductance. Next, the chip pads are individually connected to the lead frame with aluminum or gold wires.

The wire-bonding machine use.
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